27 lines
744 B
Verilog
27 lines
744 B
Verilog
// Here are two examples of $strobe failing. It appears that thread data
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// is being cleaned up too soon for the $strobe to access it.
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module test;
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reg[4:0] j;
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reg [5:0] in [1:0];
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wire [5:0] out;
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assign out = in[j]; // This uses the current j.
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initial begin
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in[1] = 6'b110001;
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j = 1;
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#1; // Need some delay for the calculations to run.
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$display("out: %b, in[%0d] %b:", out, j, in[j]);
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$display("out[3:0]: %b, in[%0d] %b:", out[j*1-1 +: 4], j, in[j]);
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// in[j] is what is failing.
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$strobe("out: %b, in[%0d] %b:", out, j, in[j]);
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// out[j... is what is failing.
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$strobe("out[3:0]: %b, in[%0d] %b:", out[j*1-1 +: 4], j, in[j]);
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// #1; // Adding this will work around the bug.
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end
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endmodule
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