26 lines
486 B
Verilog
26 lines
486 B
Verilog
module ttop;
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reg tpass = 0, fpass = 0;
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task ttop;
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#1 tpass = 1;
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endtask
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initial begin
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ttop;
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#2;
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case ({tpass, fpass})
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2'b00: $display("FAILED - both task and function test");
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2'b01: $display("FAILED - task test");
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2'b10: $display("FAILED - function test");
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2'b11: $display("PASSED");
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endcase
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end
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endmodule
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module ftop;
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function ftop;
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input a;
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ftop = ~a;
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endfunction
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initial if (ftop(0)) #1 ttop.fpass = 1;
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endmodule
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