23 lines
427 B
Verilog
23 lines
427 B
Verilog
module main;
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reg [3:0] value;
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reg [2:0] addr;
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wire test_bit = value[addr] == 1;
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initial begin
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value = 'b0110;
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for (addr = 0 ; addr < 4 ; addr = addr+1) begin
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#1 if (test_bit !== value[addr]) begin
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$display("FAILED -- value[%d]=%b, test_bit=%b",
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addr, value[addr], test_bit);
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$finish;
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end
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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