21 lines
656 B
Verilog
21 lines
656 B
Verilog
module bar;
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reg [24:1] original = 24'h123456;
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reg [8:1] second, minus_indexed, plus_indexed;
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integer tmp;
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initial begin
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second = original[16:9];
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minus_indexed = original[16 -:8];
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plus_indexed = original[9 +:8];
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$display ("Orig = %h, Second = %h, Minus Indexed = %h, Plus Indexed = %h",
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original, second, minus_indexed, plus_indexed);
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tmp = 9;
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second = original[16:9];
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minus_indexed = original[tmp+7 -:8];
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plus_indexed = original[tmp +:8];
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$display ("Orig = %h, Second = %h, Minus Indexed = %h, Plus Indexed = %h",
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original, second, minus_indexed, plus_indexed);
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end
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endmodule
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