38 lines
921 B
Verilog
38 lines
921 B
Verilog
module main;
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parameter WORD_WID = 3;
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parameter WORD_CNT = 8;
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reg [WORD_WID-1: 0] mem [0:WORD_CNT-1], tmp;
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integer idx, jdx;
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initial begin
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for (idx = 0 ; idx < WORD_CNT ; idx = idx+1)
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mem[idx] = idx;
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for (idx = 0 ; idx < WORD_CNT ; idx = idx+1) begin
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tmp = idx;
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if (mem[idx][2:1] !== tmp[2:1]) begin
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$display("FAILED -= mem[%d][2:1]=%b, tmp[2:1]=%b",
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idx, mem[idx][2:1], tmp[2:1]);
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$finish;
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end
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if (mem[idx][1:0] !== tmp[1:0]) begin
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$display("FAILED -= mem[%d][1:0]=%b, tmp[1:0]=%b",
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idx, mem[idx][1:0], tmp[1:0]);
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$finish;
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end
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for (jdx = 0 ; jdx < WORD_WID ; jdx = jdx+1)
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if (mem[idx][jdx +:2] !== tmp[jdx +:2]) begin
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$display("FAILED -- mem[%d][%d +:2]=%b, tmp[%d +:2]=%b",
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idx, jdx, mem[idx][jdx+:2], jdx, tmp[jdx+:2]);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule // main
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