22 lines
420 B
Verilog
22 lines
420 B
Verilog
module RegisterArrayBug01;
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reg [15:0] rf[0:7];
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wire [3:0] rf_0_slice0 = rf[0][3:0];
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wire [15:0] rf_0 = rf[0];
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initial begin
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$monitor($time,, "rf and slice: %h %h", rf_0, rf_0_slice0);
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rf[0] = 16'hffff;
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#10 rf[0] = 16'h0000;
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#10 rf[0] = 16'hbeef;
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#10 $finish(0);
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end
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endmodule
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/* Program fails to compile with result:
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elab_net.cc:1738: failed assertion `msb_ == 0'
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*/
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