27 lines
419 B
Verilog
27 lines
419 B
Verilog
// pr1639060
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module top;
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real value;
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initial begin
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value = 10.0;
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// value = -10.0;
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print;
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end
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task print;
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real tmp;
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begin
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if (value < 0.0) tmp = value + 10.0;
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else tmp = value;
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$display("1. The result is %5.1f", tmp);
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// This line fails!
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tmp = (value < 0.0) ? value+10.0 : value;
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$display("2. The result is %5.1f", tmp);
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end
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endtask
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endmodule
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