20 lines
352 B
Verilog
20 lines
352 B
Verilog
module test;
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reg[9:0] tst;
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initial begin
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#1 tst = 0;
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// This should set the register to 10'b00000xxxxx!
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#1 tst = 5'hxx;
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#1 tst = 10'h3ff;
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#1 tst = 10'b00000xxxxx;
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#1 tst = 0;
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#1 tst = 8'hxx;
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#1 tst = 0;
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#1 $finish(0);
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end
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always @(tst) begin
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$display("At %0t value is %b", $time, tst);
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end
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endmodule
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