45 lines
761 B
Verilog
45 lines
761 B
Verilog
module test;
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parameter SIZE = 2;
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reg [SIZE-1:0] d ; // data in
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reg c ; // latch control
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wire [SIZE-1:0] q ; // output
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unit_latch u_lat[SIZE-1:0] (.Q(q), .G(c), .D(d));
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initial begin
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d = 0;
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c = 1;
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#1 if (q !== 2'b00) begin
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$display("FAILED -- Initial load failed.");
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$finish;
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end
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d = 2'b01;
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#1 if (q !== 2'b01) begin
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$display("FAILED -- Latch follow failed.");
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$finish;
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end
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c = 0;
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#1 d = 2'b10;
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#1 if (q !== 2'b01) begin
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$display("FAILED -- Latch hold failed.");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule
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module unit_latch(output reg Q, input wire D, input wire G);
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always @*
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if (G) Q = D;
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endmodule // unit_latch
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