73 lines
1.1 KiB
Verilog
73 lines
1.1 KiB
Verilog
module test;
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reg [2:0] ptr;
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reg [2:0] size;
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reg [2:0] ptr_nxt;
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always @*
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begin
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ptr_nxt = ptr;
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if ( ptr + size > 3 )
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begin
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ptr_nxt = ptr + size - 3;
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end
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else
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begin
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ptr_nxt = 0;
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end
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end
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initial
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begin
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#1;
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ptr = 2;
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size = 2;
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#1
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$write("ptr_nxt=%0d ptr=%0d size=%0d", ptr_nxt, ptr, size);
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if ( ptr_nxt == 1 )
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begin
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$display(" OK");
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end
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else
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begin
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$display(" ERROR");
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$finish;
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end
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ptr = 3;
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size = 4;
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#1
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$write("ptr_nxt=%0d ptr=%0d size=%0d", ptr_nxt, ptr, size);
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if ( ptr_nxt == 4 )
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begin
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$display(" OK");
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end
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else
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begin
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$display(" ERROR");
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$finish;
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end
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ptr = 3;
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size = 5;
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#1
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$write("ptr_nxt=%0d ptr=%0d size=%0d", ptr_nxt, ptr, size);
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if ( ptr_nxt == 5 )
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begin
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$display(" OK");
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end
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else
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begin
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$display(" ERROR");
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$finish;
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end
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$display("PASSED");
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$finish;
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end
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endmodule
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