47 lines
799 B
Verilog
47 lines
799 B
Verilog
/*
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* This tests the handling of signed/types parameters. This is a test
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* of the complaints from pr 1449749.
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*/
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module main;
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parameter foo = -2;
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parameter integer bar = -3;
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parameter signed [5:0] bat = -7;
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initial begin
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$display("foo=%d, bar=%d, tmp=%d", foo, bar, bat);
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if (foo >= 0) begin
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$display("FAILED -- -2 > 0");
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$finish;
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end
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if (foo != -2) begin
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$display("FAILED");
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$finish;
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end
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if (bar >= 0) begin
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$display("FAILED -- -3 > 0");
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$finish;
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end
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if (bar != -3) begin
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$display("FAILED");
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$finish;
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end
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if (bat >= 0) begin
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$display("FAILED -- -7 > 0");
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$finish;
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end
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if (bat != -7) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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