17 lines
434 B
Verilog
17 lines
434 B
Verilog
module main;
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initial begin
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# 32 $display("PASSED");
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$finish;
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end
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// This delay is 'h1_00000010. The idea here is if the delay is
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// only treated as 32 bits anywhere in the processing, then the
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// high bits are truncated, and it becomes 16, which is less then
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// the 32 above and we fail.
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initial begin
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# 4294967312 $display("FAILED -- time=%d", $time);
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$finish;
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end
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endmodule // main
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