61 lines
1.4 KiB
Verilog
61 lines
1.4 KiB
Verilog
//
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// Copyright (c) 2002 Stephen Williams
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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module main;
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reg ena, wea;
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reg enb, web;
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reg clk;
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reg out = 0;
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always @(posedge clk) begin
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if ((ena == 1) && (wea == 1) &&
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(enb == 1) && (web == 1))
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out <= 1;
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end
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initial begin
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clk = 0;
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ena = 0;
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enb = 0;
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wea = 0;
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web = 0;
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$monitor("clk=%b: ena=%b, enb=%b, wea=%b, web=%b --> out=%b",
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clk, ena, enb, wea, web, out);
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#1 clk = 1;
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#1 clk = 0;
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ena = 1;
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enb = 1;
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#1 clk = 1;
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#1 clk = 0;
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wea = 1;
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web = 1;
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#1 clk = 1;
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#1 clk = 0;
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end // initial begin
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endmodule // main
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