108 lines
2.4 KiB
Verilog
108 lines
2.4 KiB
Verilog
/*
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* land3 - a verilog test for logical and operator && in a conditional.
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*
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* Copyright (C) 1999 Stephen G. Tell
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* Portions inspired by qmark.v by Steven Wilson (stevew@home.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this software; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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* Boston, MA 02111-1307 USA
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*/
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module land3;
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reg Clk;
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reg a;
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reg b;
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reg c;
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reg error;
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wire q;
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wire q_calc;
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tand tand_m(q,q_calc, a, b, c);
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initial Clk = 0;
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always #10 Clk = ~Clk;
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always @(posedge Clk)
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begin
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#1 ;
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if(q != q_calc)
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begin
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$display("FAILED - Cond && failed for vect %b%b%b - was %b, s/b %b",
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a,b,c,q,q_calc);
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error = 1;
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end
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end
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reg [3:0] bvec;
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integer xa, xb, xc;
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initial begin
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error = 0;
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bvec = 4'bzx10 ;
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for(xa = 0; xa < 4; xa = xa + 1)
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for(xb = 0; xb < 4; xb = xb + 1)
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for(xc = 0; xc < 4; xc = xc + 1)
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begin
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@(posedge Clk)
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a = bvec[xa];
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b = bvec[xb];
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c = bvec[xc];
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end // for (var3 = 0; var3 <= 3; var3 = var3 + 1)
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@(posedge Clk) ;
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@(posedge Clk) ;
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if(error == 0)
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$display("PASSED");
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$finish;
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end
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endmodule
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module tand(q, q_calc, a, b, c);
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output q;
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output q_calc;
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input a;
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input b;
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input c;
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reg q;
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reg q_calc;
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always @(a or b or c) begin
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if(a===b && b===c)
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q <= 1;
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else
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q <= 0;
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end // always @ (a or b or c)
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// Added to allow 2nd calculation
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// We use the if (a === b) formulation - it's part
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// of the base set that is need to do ANY tests..
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always @(a or b or c)
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begin
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if( a===b)
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begin
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if(b === c)
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q_calc = 1'b1;
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else
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q_calc = 1'b0;
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end
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else
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q_calc = 1'b0;
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end
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endmodule // foo
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