27 lines
324 B
Verilog
27 lines
324 B
Verilog
module dut(input [3:0] DataI, output [3:0] DataO);
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wire [3:0] DataI;
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reg [3:0] DataO;
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always @* DataO = DataI;
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endmodule
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module top();
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reg [3:0] DataI;
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wire [3:0] DataO;
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dut dut(DataI, DataO);
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initial begin
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DataI = 5;
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#1;
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if (DataO === 5)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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