luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
iverilog/ivtest/ivltests/br_gh377.v

6 lines
47 B
Verilog
Raw Blame History

module test();
parameter name = 1;
endmodule
Reference in New Issue View Git Blame Copy Permalink