53 lines
872 B
Verilog
53 lines
872 B
Verilog
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class test_t;
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typedef enum bit [1:0] { U, V } uv_t;
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uv_t foo;
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task go;
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foo = U;
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$display("test_t.foo=%b (U==0)", foo);
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if (foo !== U) begin
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$display("FAILED");
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$finish;
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end
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foo = V;
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$display("test_t.foo=%b (V==1)", foo);
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if (foo !== V) begin
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$display("FAILED");
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$finish;
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end
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endtask
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endclass // test_t
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module main;
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typedef enum bit [1:0] { X, Y } xy_t;
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xy_t foo;
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initial begin
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foo = Y;
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$display("foo=%b (Y==1)", foo);
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if (foo !== Y) begin
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$display("FAILED");
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$finish;
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end
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foo = X;
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$display("foo=%b (X==0)", foo);
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if (foo !== X) begin
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$display("FAILED");
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$finish;
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end
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end
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test_t bar;
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initial begin
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bar = new;
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bar.go();
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end
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initial begin
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#1 $display("PASSED");
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$finish;
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end
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endmodule // main
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