31 lines
404 B
Verilog
31 lines
404 B
Verilog
module sub(input [3:0] value);
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wire [3:0] array[1:0];
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reg [3:0] monitor;
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assign array[0] = $unsigned(value);
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always @(array[0]) begin
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monitor = array[0];
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end
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endmodule
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module top;
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wire [3:0] value;
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sub sub1(value);
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sub sub2(value);
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initial begin
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force value = 5;
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#0;
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if ((sub1.monitor === 5) && (sub2.monitor === 5))
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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