34 lines
566 B
Verilog
34 lines
566 B
Verilog
// Check variable selects of packed arrays with negative bounds.
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module test;
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reg failed;
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reg [-8:-1][3:0] a;
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reg signed [2:0] i;
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, \
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`"val`", exp, val); \
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failed = 1'b1; \
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end
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initial begin
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failed = 1'b0;
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a = '0;
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i = -1;
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a[i] = 4'ha;
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i = -2;
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a[i] = 4'h5;
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`check(a[-1], 4'ha);
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`check(a[-2], 4'h5);
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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