40 lines
657 B
Verilog
40 lines
657 B
Verilog
// Check that enum literals declared inside generate blocks are available in
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// the generated scope.
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module test;
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reg failed;
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`define check(val, exp) do begin \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, \
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`"val`", exp, val); \
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failed = 1'b1; \
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end \
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end while (0)
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if (1) begin : g
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typedef enum logic [3:0] {
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A = 4'd1,
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B = 4'd2
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} EN_T;
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EN_T e = A;
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initial begin
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failed = 1'b0;
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#1;
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`check(e, A);
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e = B;
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`check(e, B);
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if (!failed) begin
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$display("PASSED");
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end
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end
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end
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endmodule
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