760 lines
24 KiB
C++
760 lines
24 KiB
C++
/*
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* VHDL code generation for scopes.
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*
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* Copyright (C) 2008 Nick Gasson (nick@nickg.me.uk)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "vhdl_target.h"
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#include "vhdl_element.hh"
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#include <iostream>
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#include <sstream>
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#include <cassert>
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static string make_safe_name(ivl_signal_t sig);
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static vhdl_entity *g_active_entity = NULL;
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vhdl_entity *get_active_entity()
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{
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return g_active_entity;
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}
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void set_active_entity(vhdl_entity *ent)
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{
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g_active_entity = ent;
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}
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/*
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* This represents the portion of a nexus that is visible within
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* a VHDL scope. If that nexus portion does not contain a signal,
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* then `tmpname' gives the name of the temporary that will be
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* used when this nexus is used in `scope' (e.g. for LPMs that
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* appear in instantiations). The list `connect' lists all the
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* signals that should be joined together to re-create the net.
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*/
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struct scope_nexus_t {
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vhdl_scope *scope;
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ivl_signal_t sig; // A real signal
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string tmpname; // A new temporary signal
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list<ivl_signal_t> connect; // Other signals to wire together
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};
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/*
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* This structure is stored in the private part of each nexus.
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* It stores a scope_nexus_t for each VHDL scope which is
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* connected to that nexus. It's stored as a list so we can use
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* contained_within to allow several nested scopes to reference
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* the same signal.
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*/
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struct nexus_private_t {
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list<scope_nexus_t> signals;
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vhdl_expr *const_driver;
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};
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/*
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* Returns the scope_nexus_t of this nexus visible within scope.
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*/
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static scope_nexus_t *visible_nexus(nexus_private_t *priv, vhdl_scope *scope)
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{
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list<scope_nexus_t>::iterator it;
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for (it = priv->signals.begin(); it != priv->signals.end(); ++it) {
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if (scope->contained_within((*it).scope))
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return &*it;
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}
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return NULL;
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}
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/*
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* Remember that a signal in `scope' is part of this nexus. The
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* first signal passed to this function for a scope will be used
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* as the canonical representation of this nexus when we need to
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* convert it to a variable reference (e.g. in a LPM input/output).
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*/
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static void link_scope_to_nexus_signal(nexus_private_t *priv, vhdl_scope *scope,
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ivl_signal_t sig)
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{
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scope_nexus_t *sn;
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if ((sn = visible_nexus(priv, scope))) {
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assert(sn->tmpname == "");
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sn->connect.push_back(sig);
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}
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else {
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scope_nexus_t new_sn = { scope, sig, "" };
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priv->signals.push_back(new_sn);
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}
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}
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/*
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* Make a temporary the representative of this nexus in scope.
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*/
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static void link_scope_to_nexus_tmp(nexus_private_t *priv, vhdl_scope *scope,
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const string &name)
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{
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scope_nexus_t new_sn = { scope, NULL, name };
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priv->signals.push_back(new_sn);
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}
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/*
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* Finds the name of the nexus signal within this scope.
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*/
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static string visible_nexus_signal_name(nexus_private_t *priv, vhdl_scope *scope)
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{
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scope_nexus_t *sn = visible_nexus(priv, scope);
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assert(sn);
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return sn->sig ? get_renamed_signal(sn->sig) : sn->tmpname;
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}
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/*
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* Generates VHDL code to fully represent a nexus.
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*/
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void draw_nexus(ivl_nexus_t nexus)
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{
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nexus_private_t *priv = new nexus_private_t;
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priv->const_driver = NULL;
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int nptrs = ivl_nexus_ptrs(nexus);
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// First pass through connect all the signals up
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for (int i = 0; i < nptrs; i++) {
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ivl_nexus_ptr_t nexus_ptr = ivl_nexus_ptr(nexus, i);
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ivl_signal_t sig;
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if ((sig = ivl_nexus_ptr_sig(nexus_ptr))) {
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vhdl_scope *scope = find_scope_for_signal(sig);
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link_scope_to_nexus_signal(priv, scope, sig);
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}
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}
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// Second pass through make sure logic/LPMs have signal
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// inputs and outputs
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for (int i = 0; i < nptrs; i++) {
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ivl_nexus_ptr_t nexus_ptr = ivl_nexus_ptr(nexus, i);
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ivl_net_logic_t log;
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ivl_lpm_t lpm;
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ivl_net_const_t con;
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if ((log = ivl_nexus_ptr_log(nexus_ptr))) {
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ivl_scope_t log_scope = ivl_logic_scope(log);
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vhdl_scope *vhdl_scope =
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find_entity(ivl_scope_name(log_scope))->get_arch()->get_scope();
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if (visible_nexus(priv, vhdl_scope)) {
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// Already seen this signal in vhdl_scope
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}
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else {
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// Create a temporary signal to connect it to the nexus
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vhdl_type *type =
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vhdl_type::type_for(ivl_logic_width(log), false);
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ostringstream ss;
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ss << "LO" << ivl_logic_basename(log);
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vhdl_scope->add_decl(new vhdl_signal_decl(ss.str().c_str(), type));
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link_scope_to_nexus_tmp(priv, vhdl_scope, ss.str());
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}
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}
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else if ((lpm = ivl_nexus_ptr_lpm(nexus_ptr))) {
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ivl_scope_t lpm_scope = ivl_lpm_scope(lpm);
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vhdl_scope *vhdl_scope =
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find_entity(ivl_scope_name(lpm_scope))->get_arch()->get_scope();
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if (visible_nexus(priv, vhdl_scope)) {
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// Already seen this signal in vhdl_scope
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}
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else {
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// Create a temporary signal to connect the nexus
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// TODO: we could avoid this for IVL_LPM_PART_PV
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vhdl_type *type = vhdl_type::type_for(ivl_lpm_width(lpm),
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ivl_lpm_signed(lpm) != 0);
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ostringstream ss;
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ss << "LPM" << ivl_lpm_basename(lpm);
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vhdl_scope->add_decl(new vhdl_signal_decl(ss.str().c_str(), type));
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link_scope_to_nexus_tmp(priv, vhdl_scope, ss.str());
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}
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}
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else if ((con = ivl_nexus_ptr_con(nexus_ptr))) {
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if (ivl_const_width(con) == 1)
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priv->const_driver = new vhdl_const_bit(ivl_const_bits(con)[0]);
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else
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priv->const_driver =
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new vhdl_const_bits(ivl_const_bits(con), ivl_const_width(con),
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ivl_const_signed(con) != 0);
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}
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}
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// Save the private data in the nexus
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ivl_nexus_set_private(nexus, priv);
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}
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/*
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* Ensure that a nexus has been initialised. I.e. all the necessary
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* statements, declarations, etc. have been generated.
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*/
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static void seen_nexus(ivl_nexus_t nexus)
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{
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if (ivl_nexus_get_private(nexus) == NULL)
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draw_nexus(nexus);
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}
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/*
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* Translate a nexus to a variable reference. Given a nexus and a
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* scope, this function returns a reference to a signal that is
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* connected to the nexus and within the given scope. This signal
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* might not exist in the original Verilog source (even as a
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* compiler-generated temporary). If this nexus hasn't been
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* encountered before, the necessary code to connect up the nexus
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* will be generated.
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*/
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vhdl_var_ref *nexus_to_var_ref(vhdl_scope *scope, ivl_nexus_t nexus)
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{
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seen_nexus(nexus);
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nexus_private_t *priv =
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static_cast<nexus_private_t*>(ivl_nexus_get_private(nexus));
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string renamed(visible_nexus_signal_name(priv, scope));
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vhdl_decl *decl = scope->get_decl(renamed);
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assert(decl);
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vhdl_type *type = new vhdl_type(*(decl->get_type()));
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return new vhdl_var_ref(renamed.c_str(), type);
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}
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/*
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* Translate all the primitive logic gates into concurrent
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* signal assignments.
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*/
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static void declare_logic(vhdl_arch *arch, ivl_scope_t scope)
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{
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int nlogs = ivl_scope_logs(scope);
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for (int i = 0; i < nlogs; i++)
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draw_logic(arch, ivl_scope_log(scope, i));
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}
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/*
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* Make sure a signal name conforms to VHDL naming rules.
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*/
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static string make_safe_name(ivl_signal_t sig)
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{
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string name(ivl_signal_basename(sig));
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if (name[0] == '_')
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name.insert(0, "VL");
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const char *vhdl_reserved[] = {
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"in", "out", "entity", "architecture", "inout", "array",
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"is", "not", "and", "or", "bus", "bit", "line", // Etc...
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NULL
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};
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for (const char **p = vhdl_reserved; *p != NULL; p++) {
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if (name == *p) {
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name.insert(0, "VL_");
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break;
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}
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}
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return name;
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}
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/*
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* Declare all signals and ports for a scope.
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*/
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static void declare_signals(vhdl_entity *ent, ivl_scope_t scope)
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{
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int nsigs = ivl_scope_sigs(scope);
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for (int i = 0; i < nsigs; i++) {
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ivl_signal_t sig = ivl_scope_sig(scope, i);
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remember_signal(sig, ent->get_arch()->get_scope());
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string name(make_safe_name(sig));
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rename_signal(sig, name);
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vhdl_type *sig_type;
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unsigned dimensions = ivl_signal_dimensions(sig);
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if (dimensions > 0) {
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// Arrays are implemented by generating a separate type
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// declaration for each array, and then declaring a
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// signal of that type
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if (dimensions > 1) {
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error("> 1 dimension arrays not implemented yet");
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return;
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}
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string type_name = name + "_Type";
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vhdl_type *base_type =
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vhdl_type::type_for(ivl_signal_width(sig), ivl_signal_signed(sig) != 0);
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int lsb = ivl_signal_array_base(sig);
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int msb = lsb + ivl_signal_array_count(sig) - 1;
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vhdl_type *array_type =
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vhdl_type::array_of(base_type, type_name, msb, lsb);
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vhdl_decl *array_decl = new vhdl_type_decl(type_name.c_str(), array_type);
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ent->get_arch()->get_scope()->add_decl(array_decl);
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sig_type = new vhdl_type(*array_type);
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}
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else
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sig_type =
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vhdl_type::type_for(ivl_signal_width(sig), ivl_signal_signed(sig) != 0);
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ivl_signal_port_t mode = ivl_signal_port(sig);
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switch (mode) {
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case IVL_SIP_NONE:
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{
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vhdl_decl *decl = new vhdl_signal_decl(name.c_str(), sig_type);
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ent->get_arch()->get_scope()->add_decl(decl);
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}
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break;
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case IVL_SIP_INPUT:
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ent->get_scope()->add_decl
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(new vhdl_port_decl(name.c_str(), sig_type, VHDL_PORT_IN));
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break;
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case IVL_SIP_OUTPUT:
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{
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vhdl_port_decl *decl =
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new vhdl_port_decl(name.c_str(), sig_type, VHDL_PORT_OUT);
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ent->get_scope()->add_decl(decl);
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}
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if (ivl_signal_type(sig) == IVL_SIT_REG) {
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// A registered output
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// In Verilog the output and reg can have the
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// same name: this is not valid in VHDL
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// Instead a new signal foo_Reg is created
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// which represents the register
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std::string newname(name);
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newname += "_Reg";
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rename_signal(sig, newname.c_str());
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vhdl_type *reg_type = new vhdl_type(*sig_type);
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ent->get_arch()->get_scope()->add_decl
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(new vhdl_signal_decl(newname.c_str(), reg_type));
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// Create a concurrent assignment statement to
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// connect the register to the output
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ent->get_arch()->add_stmt
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(new vhdl_cassign_stmt
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(new vhdl_var_ref(name.c_str(), NULL),
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new vhdl_var_ref(newname.c_str(), NULL)));
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}
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break;
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case IVL_SIP_INOUT:
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ent->get_scope()->add_decl
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(new vhdl_port_decl(name.c_str(), sig_type, VHDL_PORT_INOUT));
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break;
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default:
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assert(false);
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}
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}
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}
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/*
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* Generate VHDL for LPM instances in a module.
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*/
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static void declare_lpm(vhdl_arch *arch, ivl_scope_t scope)
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{
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int nlpms = ivl_scope_lpms(scope);
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for (int i = 0; i < nlpms; i++) {
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ivl_lpm_t lpm = ivl_scope_lpm(scope, i);
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if (draw_lpm(arch, lpm) != 0)
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error("Failed to translate LPM %s", ivl_lpm_name(lpm));
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}
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}
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/*
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* Map two signals together in an instantiation.
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* The signals are joined by a nexus.
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*/
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static void map_signal(ivl_signal_t to, vhdl_entity *parent,
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vhdl_comp_inst *inst)
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{
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// TODO: Work for multiple words
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ivl_nexus_t nexus = ivl_signal_nex(to, 0);
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seen_nexus(nexus);
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vhdl_scope *arch_scope = parent->get_arch()->get_scope();
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nexus_private_t *priv =
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static_cast<nexus_private_t*>(ivl_nexus_get_private(nexus));
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assert(priv);
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if (!visible_nexus(priv, arch_scope)) {
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// This nexus isn't attached to anything in the parent
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return;
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}
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vhdl_var_ref *ref = nexus_to_var_ref(parent->get_arch()->get_scope(), nexus);
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string name = make_safe_name(to);
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// If we're mapping an output of this entity to an output of
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// the child entity, then VHDL will not let us read the value
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// of the signal (i.e. it must pass straight through).
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// However, Verilog allows the signal to be read in the parent.
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// To get around this we create an internal signal name_Sig
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// that takes the value of the output and can be read.
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vhdl_decl *decl =
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parent->get_arch()->get_scope()->get_decl(ref->get_name());
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vhdl_port_decl *pdecl;
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if ((pdecl = dynamic_cast<vhdl_port_decl*>(decl))
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&& pdecl->get_mode() == VHDL_PORT_OUT) {
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// We need to create a readable signal to shadow this output
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string shadow_name(ref->get_name());
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shadow_name += "_Sig";
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vhdl_signal_decl *shadow =
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new vhdl_signal_decl(shadow_name.c_str(),
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new vhdl_type(*decl->get_type()));
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shadow->set_comment("Needed to make output readable");
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parent->get_arch()->get_scope()->add_decl(shadow);
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// Make a continuous assignment of the shadow to the output
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parent->get_arch()->add_stmt
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(new vhdl_cassign_stmt
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(ref, new vhdl_var_ref(shadow_name.c_str(), NULL)));
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// Make sure any future references to this signal read the
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// shadow not the output
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ivl_signal_t sig = find_signal_named(ref->get_name(),
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parent->get_arch()->get_scope());
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rename_signal(sig, shadow_name);
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// Finally map the child port to the shadow signal
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inst->map_port(name.c_str(),
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new vhdl_var_ref(shadow_name.c_str(), NULL));
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}
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else {
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// Not an output port declaration therefore we can
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// definitely read it
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inst->map_port(name.c_str(), ref);
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}
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}
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/*
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* Find all the port mappings of a module instantiation.
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*/
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static void port_map(ivl_scope_t scope, vhdl_entity *parent,
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vhdl_comp_inst *inst)
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{
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// Find all the port mappings
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int nsigs = ivl_scope_sigs(scope);
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for (int i = 0; i < nsigs; i++) {
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ivl_signal_t sig = ivl_scope_sig(scope, i);
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ivl_signal_port_t mode = ivl_signal_port(sig);
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switch (mode) {
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case IVL_SIP_NONE:
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// Internal signals don't appear in the port map
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break;
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case IVL_SIP_INPUT:
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case IVL_SIP_OUTPUT:
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case IVL_SIP_INOUT:
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map_signal(sig, parent, inst);
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break;
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default:
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assert(false);
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}
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}
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}
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/*
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* Create a VHDL function from a Verilog function definition.
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*/
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static int draw_function(ivl_scope_t scope, ivl_scope_t parent)
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{
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assert(ivl_scope_type(scope) == IVL_SCT_FUNCTION);
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// Find the containing entity
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vhdl_entity *ent = find_entity(ivl_scope_name(parent));
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|
assert(ent);
|
|
|
|
const char *funcname = ivl_scope_tname(scope);
|
|
|
|
assert(!ent->get_arch()->get_scope()->have_declared(funcname));
|
|
|
|
// The return type is worked out from the output port
|
|
vhdl_function *func = new vhdl_function(funcname, NULL);
|
|
|
|
int nsigs = ivl_scope_sigs(scope);
|
|
for (int i = 0; i < nsigs; i++) {
|
|
ivl_signal_t sig = ivl_scope_sig(scope, i);
|
|
vhdl_type *sigtype =
|
|
vhdl_type::type_for(ivl_signal_width(sig),
|
|
ivl_signal_signed(sig) != 0);
|
|
|
|
string signame(make_safe_name(sig));
|
|
|
|
switch (ivl_signal_port(sig)) {
|
|
case IVL_SIP_INPUT:
|
|
func->add_param(new vhdl_param_decl(signame.c_str(), sigtype));
|
|
break;
|
|
case IVL_SIP_OUTPUT:
|
|
// The magic variable Verilog_Result holds the return value
|
|
signame = "Verilog_Result";
|
|
func->set_type(new vhdl_type(*sigtype));
|
|
default:
|
|
func->get_scope()->add_decl
|
|
(new vhdl_var_decl(signame.c_str(), sigtype));
|
|
}
|
|
|
|
remember_signal(sig, func->get_scope());
|
|
rename_signal(sig, signame);
|
|
}
|
|
|
|
// Non-blocking assignment not allowed in functions
|
|
func->get_scope()->set_allow_signal_assignment(false);
|
|
|
|
set_active_entity(ent);
|
|
{
|
|
draw_stmt(func, func->get_container(), ivl_scope_def(scope));
|
|
}
|
|
set_active_entity(NULL);
|
|
|
|
ent->get_arch()->get_scope()->add_decl(func);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Create an empty VHDL entity for a Verilog module.
|
|
*/
|
|
static void create_skeleton_entity_for(ivl_scope_t scope)
|
|
{
|
|
assert(ivl_scope_type(scope) == IVL_SCT_MODULE);
|
|
|
|
// The type name will become the entity name
|
|
const char *tname = ivl_scope_tname(scope);
|
|
|
|
// Remember the scope name this entity was derived from so
|
|
// the correct processes can be added later
|
|
const char *derived_from = ivl_scope_name(scope);
|
|
|
|
// Verilog does not have the entity/architecture distinction
|
|
// so we always create a pair and associate the architecture
|
|
// with the entity for convenience (this also means that we
|
|
// retain a 1-to-1 mapping of scope to VHDL element)
|
|
vhdl_arch *arch = new vhdl_arch(tname, "FromVerilog");
|
|
vhdl_entity *ent = new vhdl_entity(tname, derived_from, arch);
|
|
|
|
// Build a comment to add to the entity/architecture
|
|
ostringstream ss;
|
|
ss << "Generated from Verilog module " << ivl_scope_tname(scope);
|
|
|
|
arch->set_comment(ss.str());
|
|
ent->set_comment(ss.str());
|
|
|
|
remember_entity(ent);
|
|
}
|
|
|
|
/*
|
|
* A first pass through the hierarchy: create VHDL entities for
|
|
* each unique Verilog module type.
|
|
*/
|
|
static int draw_skeleton_scope(ivl_scope_t scope, void *_parent)
|
|
{
|
|
if (ivl_scope_type(scope) == IVL_SCT_MODULE)
|
|
create_skeleton_entity_for(scope);
|
|
|
|
return ivl_scope_children(scope, draw_skeleton_scope, scope);
|
|
}
|
|
|
|
static int draw_all_signals(ivl_scope_t scope, void *_parent)
|
|
{
|
|
if (ivl_scope_type(scope) == IVL_SCT_MODULE) {
|
|
vhdl_entity *ent = find_entity(ivl_scope_name(scope));
|
|
assert(ent);
|
|
|
|
declare_signals(ent, scope);
|
|
}
|
|
|
|
return ivl_scope_children(scope, draw_all_signals, scope);
|
|
}
|
|
|
|
/*
|
|
* Draw all tasks and functions in the hierarchy.
|
|
*/
|
|
static int draw_functions(ivl_scope_t scope, void *_parent)
|
|
{
|
|
ivl_scope_t parent = static_cast<ivl_scope_t>(_parent);
|
|
if (ivl_scope_type(scope) == IVL_SCT_FUNCTION) {
|
|
vhdl_entity *ent = find_entity(ivl_scope_name(parent));
|
|
assert(ent);
|
|
|
|
if (draw_function(scope, parent) != 0)
|
|
return 1;
|
|
}
|
|
|
|
return ivl_scope_children(scope, draw_functions, scope);
|
|
}
|
|
|
|
/*
|
|
* Make concurrent assignments for constants in nets. This works
|
|
* bottom-up so that the driver is in the lowest instance it can.
|
|
* This also has the side effect of generating all the necessary
|
|
* nexus code.
|
|
*/
|
|
static int draw_constant_drivers(ivl_scope_t scope, void *_parent)
|
|
{
|
|
ivl_scope_children(scope, draw_constant_drivers, scope);
|
|
|
|
if (ivl_scope_type(scope) == IVL_SCT_MODULE) {
|
|
vhdl_entity *ent = find_entity(ivl_scope_name(scope));
|
|
assert(ent);
|
|
|
|
int nsigs = ivl_scope_sigs(scope);
|
|
for (int i = 0; i < nsigs; i++) {
|
|
ivl_signal_t sig = ivl_scope_sig(scope, i);
|
|
|
|
for (unsigned i = ivl_signal_array_base(sig);
|
|
i < ivl_signal_array_count(sig);
|
|
i++) {
|
|
// Make sure the nexus code is generated
|
|
ivl_nexus_t nex = ivl_signal_nex(sig, i);
|
|
seen_nexus(nex);
|
|
|
|
nexus_private_t *priv =
|
|
static_cast<nexus_private_t*>(ivl_nexus_get_private(nex));
|
|
assert(priv);
|
|
|
|
vhdl_scope *arch_scope = ent->get_arch()->get_scope();
|
|
|
|
if (priv->const_driver) {
|
|
assert(i == 0); // TODO: Make work for more words
|
|
|
|
vhdl_var_ref *ref = nexus_to_var_ref(arch_scope, nex);
|
|
|
|
ent->get_arch()->add_stmt
|
|
(new vhdl_cassign_stmt(ref, priv->const_driver));
|
|
priv->const_driver = NULL;
|
|
}
|
|
|
|
scope_nexus_t *sn = visible_nexus(priv, arch_scope);
|
|
for (list<ivl_signal_t>::const_iterator it = sn->connect.begin();
|
|
it != sn->connect.end();
|
|
++it) {
|
|
vhdl_var_ref *rref =
|
|
new vhdl_var_ref(get_renamed_signal(sn->sig).c_str(), NULL);
|
|
vhdl_var_ref *lref =
|
|
new vhdl_var_ref(get_renamed_signal(*it).c_str(), NULL);
|
|
ent->get_arch()->add_stmt(new vhdl_cassign_stmt(lref, rref));
|
|
}
|
|
sn->connect.clear();
|
|
}
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int draw_all_logic_and_lpm(ivl_scope_t scope, void *_parent)
|
|
{
|
|
if (ivl_scope_type(scope) == IVL_SCT_MODULE) {
|
|
vhdl_entity *ent = find_entity(ivl_scope_name(scope));
|
|
assert(ent);
|
|
|
|
set_active_entity(ent);
|
|
{
|
|
declare_logic(ent->get_arch(), scope);
|
|
declare_lpm(ent->get_arch(), scope);
|
|
}
|
|
set_active_entity(NULL);
|
|
}
|
|
|
|
return ivl_scope_children(scope, draw_all_logic_and_lpm, scope);
|
|
}
|
|
|
|
static int draw_hierarchy(ivl_scope_t scope, void *_parent)
|
|
{
|
|
if (ivl_scope_type(scope) == IVL_SCT_MODULE && _parent) {
|
|
ivl_scope_t parent = static_cast<ivl_scope_t>(_parent);
|
|
|
|
vhdl_entity *ent = find_entity(ivl_scope_name(scope));
|
|
assert(ent);
|
|
|
|
vhdl_entity *parent_ent = find_entity(ivl_scope_name(parent));
|
|
assert(parent_ent);
|
|
|
|
vhdl_arch *parent_arch = parent_ent->get_arch();
|
|
assert(parent_arch != NULL);
|
|
|
|
// Create a forward declaration for it
|
|
if (!parent_arch->get_scope()->have_declared(ent->get_name())) {
|
|
vhdl_decl *comp_decl = vhdl_component_decl::component_decl_for(ent);
|
|
parent_arch->get_scope()->add_decl(comp_decl);
|
|
}
|
|
|
|
// And an instantiation statement
|
|
string inst_name(ivl_scope_basename(scope));
|
|
if (inst_name == ent->get_name()) {
|
|
// Cannot have instance name the same as type in VHDL
|
|
inst_name += "_Inst";
|
|
}
|
|
|
|
// Need to replace any [ and ] characters that result
|
|
// from generate statements
|
|
string::size_type loc = inst_name.find('[', 0);
|
|
if (loc != string::npos)
|
|
inst_name.erase(loc, 1);
|
|
|
|
loc = inst_name.find(']', 0);
|
|
if (loc != string::npos)
|
|
inst_name.erase(loc, 1);
|
|
|
|
vhdl_comp_inst *inst =
|
|
new vhdl_comp_inst(inst_name.c_str(), ent->get_name().c_str());
|
|
port_map(scope, parent_ent, inst);
|
|
|
|
parent_arch->add_stmt(inst);
|
|
}
|
|
|
|
return ivl_scope_children(scope, draw_hierarchy, scope);
|
|
}
|
|
|
|
int draw_scope(ivl_scope_t scope, void *_parent)
|
|
{
|
|
int rc = draw_skeleton_scope(scope, _parent);
|
|
if (rc != 0)
|
|
return rc;
|
|
|
|
rc = draw_all_signals(scope, _parent);
|
|
if (rc != 0)
|
|
return rc;
|
|
|
|
rc = draw_all_logic_and_lpm(scope, _parent);
|
|
if (rc != 0)
|
|
return rc;
|
|
|
|
rc = draw_hierarchy(scope, _parent);
|
|
if (rc != 0)
|
|
return rc;
|
|
|
|
rc = draw_functions(scope, _parent);
|
|
if (rc != 0)
|
|
return rc;
|
|
|
|
rc = draw_constant_drivers(scope, _parent);
|
|
if (rc != 0)
|
|
return rc;
|
|
|
|
return 0;
|
|
}
|
|
|