406 lines
11 KiB
C++
406 lines
11 KiB
C++
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const char COPYRIGHT[] =
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"Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com)";
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/*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT) && !defined(macintosh)
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#ident "$Id: main.cc,v 1.32 2000/05/03 22:14:31 steve Exp $"
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#endif
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const char NOTICE[] =
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" This program is free software; you can redistribute it and/or modify\n"
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" it under the terms of the GNU General Public License as published by\n"
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" the Free Software Foundation; either version 2 of the License, or\n"
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" (at your option) any later version.\n"
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"\n"
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" This program is distributed in the hope that it will be useful,\n"
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" but WITHOUT ANY WARRANTY; without even the implied warranty of\n"
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" MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n"
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" GNU General Public License for more details.\n"
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"\n"
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" You should have received a copy of the GNU General Public License\n"
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" along with this program; if not, write to the Free Software\n"
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" Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA\n"
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;
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# include <stdio.h>
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# include <iostream.h>
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# include <fstream>
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# include <queue>
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# include <map>
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# include <unistd.h>
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#if defined(HAVE_GETOPT_H)
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# include <getopt.h>
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#endif
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# include "pform.h"
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# include "netlist.h"
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# include "target.h"
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# include "compiler.h"
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const char VERSION[] = "$Name: $ $State: Exp $";
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const char*target = "null";
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string start_module = "";
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map<string,string> flags;
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/*
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* These are the warning enable flags.
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*/
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bool warn_implicit = false;
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static void parm_to_flagmap(const string&flag)
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{
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string key, value;
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unsigned off = flag.find('=');
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if (off > flag.size()) {
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key = flag;
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value = "";
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} else {
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key = flag.substr(0, off);
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value = flag.substr(off+1);
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}
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flags[key] = value;
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}
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extern Design* elaborate(const map<string,Module*>&modules,
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const map<string,PUdp*>&primitives,
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const string&root);
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extern void cprop(Design*des);
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extern void propinit(Design*des);
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extern void synth(Design*des);
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extern void nobufz(Design*des);
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extern void nodangle(Design*des);
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extern void xnfio(Design*des);
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typedef void (*net_func)(Design*);
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static struct net_func_map {
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const char*name;
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void (*func)(Design*);
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} func_table[] = {
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{ "cprop", &cprop },
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{ "nobufz", &nobufz },
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{ "nodangle",&nodangle },
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{ "propinit",&propinit },
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{ "synth", &synth },
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{ "xnfio", &xnfio },
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{ 0, 0 }
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};
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net_func name_to_net_func(const string&name)
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{
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for (unsigned idx = 0 ; func_table[idx].name ; idx += 1)
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if (name == func_table[idx].name)
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return func_table[idx].func;
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return 0;
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}
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int main(int argc, char*argv[])
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{
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bool help_flag = false;
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const char* net_path = 0;
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const char* out_path = 0;
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const char* pf_path = 0;
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const char* warn_en = "";
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int opt;
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unsigned flag_errors = 0;
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queue<net_func> net_func_queue;
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flags["VPI_MODULE_LIST"] = "system";
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while ((opt = getopt(argc, argv, "F:f:hm:N:o:P:s:t:vW:")) != EOF) switch (opt) {
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case 'F': {
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net_func tmp = name_to_net_func(optarg);
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if (tmp == 0) {
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cerr << "No such design transform function ``"
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<< optarg << "''." << endl;
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flag_errors += 1;
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break;
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}
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net_func_queue.push(tmp);
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break;
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}
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case 'f':
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parm_to_flagmap(optarg);
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break;
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case 'h':
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help_flag = true;
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break;
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case 'm':
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flags["VPI_MODULE_LIST"] = flags["VPI_MODULE_LIST"]+","+optarg;
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break;
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case 'N':
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net_path = optarg;
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break;
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case 'o':
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out_path = optarg;
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break;
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case 'P':
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pf_path = optarg;
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break;
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case 's':
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start_module = optarg;
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break;
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case 't':
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target = optarg;
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break;
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case 'v':
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cout << "Icarus Verilog version " << VERSION << endl;
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cout << COPYRIGHT << endl;
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cout << endl << NOTICE << endl;
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return 0;
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case 'W':
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warn_en = optarg;
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break;
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default:
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flag_errors += 1;
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break;
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}
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if (flag_errors)
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return flag_errors;
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if (help_flag) {
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cout << "Netlist functions:" << endl;
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for (unsigned idx = 0 ; func_table[idx].name ; idx += 1)
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cout << " " << func_table[idx].name << endl;
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cout << "Target types:" << endl;
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for (unsigned idx = 0 ; target_table[idx] ; idx += 1)
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cout << " " << target_table[idx]->name << endl;
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return 0;
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}
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if (optind == argc) {
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cerr << "No input files." << endl;
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return 1;
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}
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/* Scan the warnings enable string for warning flags. */
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for (const char*cp = warn_en ; *cp ; cp += 1) switch (*cp) {
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case 'i':
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warn_implicit = true;
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break;
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default:
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break;
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}
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/* Parse the input. Make the pform. */
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map<string,Module*> modules;
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map<string,PUdp*> primitives;
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int rc = pform_parse(argv[optind], modules, primitives);
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if (pf_path) {
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ofstream out (pf_path);
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out << "PFORM DUMP MODULES:" << endl;
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for (map<string,Module*>::iterator mod = modules.begin()
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; mod != modules.end()
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; mod ++ ) {
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pform_dump(out, (*mod).second);
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}
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out << "PFORM DUMP PRIMITIVES:" << endl;
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for (map<string,PUdp*>::iterator idx = primitives.begin()
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; idx != primitives.end()
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; idx ++ ) {
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(*idx).second->dump(out);
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}
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}
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if (rc) {
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return rc;
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}
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if (start_module == "") {
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for (map<string,Module*>::iterator mod = modules.begin()
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; mod != modules.end()
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; mod ++ ) {
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Module*cur = (*mod).second;
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if (cur->port_count() == 0)
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if (start_module == "") {
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start_module = cur->get_name();
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} else {
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cerr << "More then 1 top level module."
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<< endl;
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return 1;
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}
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}
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}
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/* Select a root module, and elaborate the design. */
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if (start_module == "") {
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cerr << "No top level modules, and no -s option." << endl;
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return 1;
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}
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Design*des = elaborate(modules, primitives, start_module);
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if (des == 0) {
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cerr << "Unable to elaborate module " << start_module <<
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"." << endl;
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return 1;
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}
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if (des->errors) {
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cerr << des->errors << " error(s) elaborating design." << endl;
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return des->errors;
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}
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des->set_flags(flags);
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while (!net_func_queue.empty()) {
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net_func func = net_func_queue.front();
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net_func_queue.pop();
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func(des);
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}
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if (net_path) {
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ofstream out (net_path);
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des->dump(out);
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}
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bool emit_rc;
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if (out_path) {
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ofstream out;
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out.open(out_path);
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if (! out.is_open()) {
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cerr << "Unable to open " << out_path << " for writing."
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<< endl;
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return 1;
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}
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emit_rc = emit(out, des, target);
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} else {
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emit_rc = emit(cout, des, target);
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}
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if (!emit_rc) {
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cerr << "internal error: Code generation had errors." << endl;
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return 1;
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}
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return 0;
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}
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/*
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* $Log: main.cc,v $
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* Revision 1.32 2000/05/03 22:14:31 steve
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* More features of ivl available through iverilog.
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*
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* Revision 1.31 2000/04/12 20:02:53 steve
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* Finally remove the NetNEvent and NetPEvent classes,
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* Get synthesis working with the NetEvWait class,
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* and get started supporting multiple events in a
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* wait in vvm.
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*
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* Revision 1.30 2000/03/17 21:50:25 steve
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* Switch to control warnings.
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*
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* Revision 1.29 2000/02/23 02:56:54 steve
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* Macintosh compilers do not support ident.
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*
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* Revision 1.28 2000/01/13 05:11:25 steve
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* Support for multiple VPI modules.
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*
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* Revision 1.27 1999/12/30 17:37:14 steve
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* Remove the now useless sigfold functor.
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*
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* Revision 1.26 1999/11/29 17:02:21 steve
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* include getopt if present.
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*
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* Revision 1.25 1999/11/18 03:52:19 steve
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* Turn NetTmp objects into normal local NetNet objects,
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* and add the nodangle functor to clean up the local
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* symbols generated by elaboration and other steps.
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*
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* Revision 1.24 1999/11/01 02:07:40 steve
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* Add the synth functor to do generic synthesis
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* and add the LPM_FF device to handle rows of
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* flip-flops.
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*
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* Revision 1.23 1999/09/22 16:57:23 steve
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* Catch parallel blocks in vvm emit.
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*
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* Revision 1.22 1999/08/03 04:14:49 steve
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* Parse into pform arbitrarily complex module
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* port declarations.
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*
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* Revision 1.21 1999/07/18 05:52:46 steve
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* xnfsyn generates DFF objects for XNF output, and
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* properly rewrites the Design netlist in the process.
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*
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* Revision 1.20 1999/07/17 22:01:13 steve
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* Add the functor interface for functor transforms.
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*
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* Revision 1.19 1999/07/10 23:29:21 steve
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* pform even on parse errors.
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*
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* Revision 1.18 1999/06/19 03:46:42 steve
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* Add the -v switch.
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*
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* Revision 1.17 1999/06/17 05:33:12 steve
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* Redundant declaration of pform_parse.
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*
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* Revision 1.16 1999/06/15 03:44:53 steve
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* Get rid of the STL vector template.
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*
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* Revision 1.15 1999/05/05 03:27:15 steve
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* More intelligent selection of module to elaborate.
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*
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* Revision 1.14 1999/04/23 04:34:32 steve
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* Make debug output file parameters.
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*
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* Revision 1.13 1999/02/01 00:26:49 steve
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* Carry some line info to the netlist,
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* Dump line numbers for processes.
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* Elaborate prints errors about port vector
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* width mismatch
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* Emit better handles null statements.
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*
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* Revision 1.12 1999/01/24 01:35:36 steve
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* Support null target for generating no output.
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*
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* Revision 1.11 1998/12/20 02:05:41 steve
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* Function to calculate wire initial value.
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*
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* Revision 1.10 1998/12/09 04:02:47 steve
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* Support the include directive.
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*
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* Revision 1.9 1998/12/07 04:53:17 steve
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* Generate OBUF or IBUF attributes (and the gates
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* to garry them) where a wire is a pad. This involved
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* figuring out enough of the netlist to know when such
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* was needed, and to generate new gates and signales
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* to handle what's missing.
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*
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* Revision 1.8 1998/12/02 04:37:13 steve
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* Add the nobufz function to eliminate bufz objects,
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* Object links are marked with direction,
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* constant propagation is more careful will wide links,
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* Signal folding is aware of attributes, and
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* the XNF target can dump UDP objects based on LCA
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* attributes.
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*/
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