39 lines
593 B
Verilog
39 lines
593 B
Verilog
// Regression: dynamic array and()/or()/xor() reductions (LRM 7.12.3).
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module top;
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bit failed = 0;
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`define CHK(cond) \
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if (!(cond)) begin \
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$display("FAILED line %0d", `__LINE__); \
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failed = 1; \
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end
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byte b[];
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int y;
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initial begin
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b = '{1, 3, 5, 7};
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y = b.and;
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`CHK(y === 1);
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b = '{1, 2, 3, 4};
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y = b.or;
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`CHK(y === 7);
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y = b.xor;
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`CHK(y === 4);
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b = new[0];
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y = b.and;
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`CHK(y === -1);
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y = b.or;
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`CHK(y === 0);
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y = b.xor;
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`CHK(y === 0);
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if (!failed)
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$display("PASSED");
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end
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endmodule
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