52 lines
1.1 KiB
Verilog
52 lines
1.1 KiB
Verilog
module top (
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);
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reg signed [13:0] datain;
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wire signed [15:0] dataout;
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assign dataout = datain >>> 2;
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reg test_failed;
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wire signed [15:0] expected_dataout;
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assign expected_dataout = ($signed({datain[13:2], 2'b0}) / 4) ;
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task check_data;
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if (expected_dataout != dataout)
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begin
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$display("datain = %d dataout = %h expected = %h ... CHECK FAILED", datain, dataout, expected_dataout);
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test_failed = 1;
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end
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else
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$display("datain = %d dataout = %d expected = %d ... CHECK PASSED", datain, dataout, expected_dataout);
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endtask
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initial
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begin
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test_failed = 0;
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#1 datain = 14'h0FFF;
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#0 check_data; // #0 delay to allow the wire to resolve
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#1 datain = 14'h0000;
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#0 check_data;
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#1 datain = 14'h1FFF;
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#0 check_data;
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#1 datain = 14'h1000;
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#0 check_data;
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#1 datain = 14'h2FFF;
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#0 check_data;
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#1 datain = 14'h2000;
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#0 check_data;
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#1 datain = 14'h3FFF;
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#0 check_data;
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#1 datain = 14'h3000;
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#0 check_data;
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#2;
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if (test_failed)
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$display("TEST FAILED :-(");
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else
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$display("TEST PASSED :-)");
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end
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endmodule // top
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