45 lines
763 B
Verilog
45 lines
763 B
Verilog
// Check that continuous assignments to unpacked arrays preserve delay.
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module test;
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reg failed;
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wire delayed[0:1];
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reg value[0:1];
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assign #5 delayed = value;
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`define check(val, exp) \
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if (val !== exp) begin \
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$display("FAILED(%0d). '%s' expected %b, got %b", `__LINE__, \
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`"val`", exp, val); \
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failed = 1'b1; \
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end
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initial begin
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failed = 1'b0;
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value[0] = 1'b1;
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value[1] = 1'b0;
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#5;
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`check(delayed[0], 1'b1)
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`check(delayed[1], 1'b0)
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value[0] = 1'b0;
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value[1] = 1'b1;
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#4;
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`check(delayed[0], 1'b1)
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`check(delayed[1], 1'b0)
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#1;
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`check(delayed[0], 1'b0)
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`check(delayed[1], 1'b1)
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if (!failed) begin
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$display("PASSED");
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end
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end
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endmodule
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