99 lines
3.8 KiB
Plaintext
99 lines
3.8 KiB
Plaintext
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WHAT IS XNF
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XNF is the Xilinx Netlist Format. This is somewhat specific to the
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Xilinx tool chain, but it is sufficiently ubiquitous that it's still
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worth it. This format can be fed to place and route tools and
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simulators. Since some third party simulators accept XNF, the format
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may be useful even independent of Xilinx parts.
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Icarus Verilog supports XNF as specified by the Xilinx Netlist Format
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Specification, Version 6.1.
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IVL SUPPORT FOR XNF
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Icarus Verilog has a code generator and synthesis functions that
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support generation of XNF netlists. The XNF modules also allow the
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programmer to use $attributes to control certain aspects of code
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generation.
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XNF code generation is enabled with the ``-t xnf'' flag on the command
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line. The code generator needs to know the type of part to generate
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code for, so the ``-fpart=<type>'' flag is also needed. For example,
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to generate code for the 4010E the command line might start out as:
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ivl -txnf -fpart=4010e -Fxnfsyn -Fsigfold -Fxnfio [...]
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Icarus Verilog includes the functions ``xnfsyn'' and ``xnfio'' to
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perform transformations and optimizations on the design before code is
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generated. The xnfsyn function matches certain behavioral constructs
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to XNF components, and the xnfio function generates pads and fills the
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IOBs.
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XNFSYN FUNCTION
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This function does synthesis transformations on the entered design,
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making it possible to generate XNF netlist components from certain
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behavioral constructs. This is needed in Verilog for example to model
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some of the synchronous components of the XNF library.
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It is a bit much to expect a Verilog compiler in general to generate
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components from arbitrary behavioral descriptions, so the xnfsyn
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function works by matching statements that have some documented
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structure, and substituting them for the equivalent XNF component. A
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fully synthesize-able design, then, is one where the behavioral
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statements can all be matched and substituted by the xnfsyn function.
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XNFIO FUNCTION
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The "xnfio" function transforms the netlist where the IOBs are
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concerned. The signals with PAD attributes are checked, and
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surrounding circuitry generated to conform to the logic available in
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the IOB.
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If the pad is an OPAD, the function will look for an existing buf or
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not gate connected to the PAD signal. If the gate is appropriately
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connected, the buf or not gate will be turned into an OBUF. This pulls
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the buf or inverter into the IOB, freeing a CLB and providing the
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required pin circuitry.
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If the pad is an IPAD, the function will look for a buf, and convert
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that to an IBUF. Since Xilinx IOBs cannot invert the output from an
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IBUF, NOT gates cannot be absorbed as in the OPAD case.
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/*
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* Copyright (c) 1998-1999 Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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$Log: xnf.txt,v $
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Revision 1.4 1999/08/14 22:48:21 steve
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Mention the sigfold function.
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Revision 1.3 1999/07/22 02:05:20 steve
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is_constant method for PEConcat.
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Revision 1.2 1999/07/18 21:17:51 steve
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Add support for CE input to XNF DFF, and do
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complete cleanup of replaced design nodes.
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Revision 1.1 1999/05/01 02:57:11 steve
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XNF target documentation.
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