luke
/
iverilog
mirror of https://github.com/steveicarus/iverilog.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
iverilog/ivtest/vpi/getp.v

6 lines
68 B
Verilog
Raw Blame History

module test;
initial begin
$mytest(1,9.6,3);
end
endmodule
Reference in New Issue View Git Blame Copy Permalink