31 lines
567 B
Verilog
31 lines
567 B
Verilog
// A simple generate example for VHDL conversion
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module main();
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wire [39:0] data;
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integer j;
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generate
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genvar i;
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for (i = 0; i < 4; i = i + 1) begin
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inc u(data[(i+1)*8 - 1:i*8], data[(i+2)*8 - 1:(i+1)*8]);
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end
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endgenerate
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assign data[7:0] = 1;
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initial begin
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#1;
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$display(data[7:0]);
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$display(data[15:8]);
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$display(data[23:16]);
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$display(data[31:24]);
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$display(data[39:32]);
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end
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endmodule // simple_gen
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module inc(in, out);
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input [7:0] in;
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output [7:0] out;
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assign out = in + 1;
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endmodule // inc
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