81 lines
1.4 KiB
Verilog
81 lines
1.4 KiB
Verilog
// This slightly convoluted module used to cause an argument-size
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// mismatch in the call to the function extend_data
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module test (c);
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parameter MAX_SIZE = 32;
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input c;
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reg [MAX_SIZE-1:0] d,
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e,
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f;
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reg [7:0] g;
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wire h;
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always @(posedge h or negedge c)
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if (~c)
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f <= #2 {MAX_SIZE{1'b0}};
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else
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case (g)
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8'h18 :
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f <= #2 hw(d, e);
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default :
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f <= #2 {MAX_SIZE{1'b0}};
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endcase
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parameter FALSE_RESULT = {MAX_SIZE{1'b0}},
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TRUE_RESULT = FALSE_RESULT | 1'b1;
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function integer sign_of;
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input [2*MAX_SIZE-1:0] data;
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input size;
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reg [2*MAX_SIZE-1:0] data;
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integer size;
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if (data[size-1]===1'b1)
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sign_of = -1;
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else
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sign_of = 1;
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endfunction
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function [2*MAX_SIZE-1:0] extend_data;
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input [2*MAX_SIZE-1:0] data;
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input size;
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input new_size;
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input extend;
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reg [2*MAX_SIZE-1:0] data;
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integer size,
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new_size;
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reg extend;
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for (extend_data = data ; new_size-size>0 ; new_size=new_size-1)
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extend_data[new_size-1] = extend & data[size-1];
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endfunction
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function [MAX_SIZE-1:0] hw;
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input [MAX_SIZE-1:0] a;
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input [MAX_SIZE-1:0] b;
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reg [MAX_SIZE-1:0] a,
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b;
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reg [MAX_SIZE:0] diff;
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begin
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diff = extend_data(b, MAX_SIZE, MAX_SIZE+1, 1'b1) -
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extend_data(a, MAX_SIZE, MAX_SIZE+1, 1'b1);
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if (sign_of(diff, MAX_SIZE+1)==-1)
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hw = TRUE_RESULT;
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else
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hw = FALSE_RESULT;
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end
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endfunction
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endmodule
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