22 lines
410 B
Verilog
22 lines
410 B
Verilog
// This is a simple test of automatic functions
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module autof();
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reg [7:0] result;
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function automatic [7:0] fact;
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input [7:0] n;
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if (n == 0)
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fact = 1;
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else
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fact = n * fact(n-1);
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endfunction // fact
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initial begin
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result = fact(4);
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if (result == 24)
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$display("PASSED");
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else
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$display("FAILED -- Expected 24 but got %d", result);
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end
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endmodule // autof
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