32 lines
553 B
Verilog
32 lines
553 B
Verilog
module top;
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reg [4:1] res;
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reg pass;
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initial begin
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pass = 1'b1;
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res = 4'b0000;
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fork
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#3 res[3] = 1'b1;
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#4 res[4] = 1'b1;
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join_none
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fork
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#1 res[1] = 1'b1;
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#2 res[2] = 1'b1;
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join_any
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if (res != 4'b0001) begin
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$display("Error: Only first process should have run: %b", res);
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pass = 1'b0;
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end
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wait fork;
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if (res != 4'b1111) begin
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$display("Error: All processes should have run: %b", res);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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