63 lines
1.0 KiB
Verilog
63 lines
1.0 KiB
Verilog
module stimulus (output reg A);
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initial begin
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// input is x
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#0 A = 1'bx;
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// input is z
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#10 A = 1'bz;
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// one input is a zero
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#10 A = 1'b0;
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// one input is a one
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#10 A = 1'b1;
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end
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endmodule
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module scoreboard (input Y, A);
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function truth_table (input a);
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reg gate_operand;
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reg gate_output;
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begin
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gate_operand = a;
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case (gate_operand)
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// input is x
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1'bx: gate_output = 1'bx;
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// inputs is z
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1'bz: gate_output = 1'bx;
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// normal operation on bit
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1'b0: gate_output = 1;
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1'b1: gate_output = 0;
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endcase
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truth_table = gate_output;
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end
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endfunction
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reg Y_t;
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always @(A) begin
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Y_t = truth_table (A);
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#1;
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if (Y_t !== Y) begin
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$display("FAILED! - mismatch found for input %b in NOT operation", A);
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$finish;
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end
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end
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endmodule
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module test;
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stimulus stim (A);
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not_gate duv (.a_i(A), .c_o(Y) );
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scoreboard mon (Y, A);
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initial begin
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#200;
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$display("PASSED");
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$finish;
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end
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endmodule
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