47 lines
857 B
Verilog
47 lines
857 B
Verilog
module stimulus (output reg A, B);
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reg unsigned [1:0] stimulus_count = 2'b0;
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initial begin
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{A, B} = 2'b00;
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#10 {A, B} = 2'b01;
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#10 {A, B} = 2'b10;
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#10 {A, B} = 2'b11;
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end
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endmodule
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module scoreboard (input Y, A, B);
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reg [3:0] truth_table;
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reg Y_s;
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initial begin
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truth_table['b00] = 0;
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truth_table['b01] = 0;
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truth_table['b10] = 0;
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truth_table['b11] = 1;
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end
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always @(A or B) begin
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Y_s = truth_table[{A,B}];
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#1;
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//$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
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if (Y_s !== Y) begin
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$display("FAILED! - mismatch found for inputs %b and %b", A, B);
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$finish;
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end
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end
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endmodule
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module test;
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stimulus stim (A, B);
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and_gate duv (.a_i(A), .b_i(B), .c_o(Y) );
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scoreboard mon (Y, A, B);
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initial begin
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#100 $display("PASSED");
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$finish;
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end
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endmodule
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