70 lines
1.7 KiB
Verilog
70 lines
1.7 KiB
Verilog
//
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// Copyright (c) 1999 Steven Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - Validate declared wire and implicit wires displayed.
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//
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// This circuit has 3 i/os and 3 implicit wires. Both should be
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// present in vcd file??
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module xorckt (out,in0,in1);
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input in0;
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input in1;
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wire junk;
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nand #1 na1 (na1_out,in0,in1);
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nand #1 na2 (na2_out,in0,na1_out);
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nand #1 na3 (na3_out,in1,na1_out);
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nand #1 na4 (out,na2_out,na3_out);
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assign junk = in0;
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endmodule
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module main;
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wire xout;
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reg i1,i2;
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xorckt myckt (.out(xout),.in0(i1),.in1(i2));
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initial
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begin
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$dumpfile("work/test.vcd");
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$dumpvars(0,main.myckt);
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i1 = 1'b0;
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i2 = 1'b0;
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#5;
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$display("%b xor %b = %b",i1,i2,xout);
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i1 = 1'b1;
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i2 = 1'b0;
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#5;
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$display("%b xor %b = %b",i1,i2,xout);
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i1 = 1'b1;
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i2 = 1'b1;
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#5;
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$display("%b xor %b = %b",i1,i2,xout);
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i1 = 1'b0;
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i2 = 1'b1;
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#5 ;
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$display("%b xor %b = %b",i1,i2,xout);
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end
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endmodule // main
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