58 lines
1.3 KiB
Verilog
58 lines
1.3 KiB
Verilog
/*
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* Some more detailed tests of the abs() function.
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*
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* Copyright (C) 2007-2008 Cary R. (cygcary@yahoo.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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module main;
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reg signed [7:0] a, b;
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initial begin
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a = 1;
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b = -1;
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if (abs(0) !== 0) begin
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$display("FAILED");
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$finish;
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end
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if (abs(1) !== 1) begin
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$display("FAILED");
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$finish;
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end
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if (abs(-1) !== 1) begin
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$display("FAILED");
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$finish;
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end
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if (abs(a) !== 1) begin
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$display("FAILED");
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$finish;
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end
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if (abs(b) !== 1) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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