28 lines
577 B
Verilog
28 lines
577 B
Verilog
`ifdef __ICARUS__
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`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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`endif
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module top;
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reg pass;
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reg [1:-1][3:0] vec;
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initial begin
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pass = 1'b1;
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vec[1] = 4'bxxxx;
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vec[0] = 4'bxxxx;
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vec[-1] = 4'bxxxx;
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`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
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vec[1'bx] = 4'b1001;
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`endif
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if ((vec[1] !== 4'bxxx) && (vec[0] !== 4'bxxxx) &&
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(vec[-1] !== 4'bxxxx)) begin
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$display("Failed vec[1'bx], expected 4'bxxxx, got %b, %b,%b",
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vec[1], vec[0], vec[-1]);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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