63 lines
1.5 KiB
Verilog
63 lines
1.5 KiB
Verilog
//
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// Copyright (c) 2001 Steve Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// SDW - From PR 272 reported by Lennart Augustsson <augustss@augustsson.net>
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module test;
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reg clk;
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reg [31:0] x;
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reg [31:0] y;
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reg error;
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always@(posedge clk)
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x <= -y;
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always #2 clk = ~clk;
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initial
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begin
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clk = 0;
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error = 0;
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y = 0;
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#10;
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if( x !== 32'h0)
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begin
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error = 1;
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$display("FAILED - X should still be 0, and it's not");
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end
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#10;
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y = 32'h11111111;
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#10;
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if(x !== 32'heeee_eeef)
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begin
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error = 1;
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$display("FAILED - X should still be EEEE_EEEF, rather x=%h",x);
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end
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#10;
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if(error == 0)
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$display("PASSED");
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$finish ;
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end
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endmodule
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