36 lines
834 B
Verilog
36 lines
834 B
Verilog
module top;
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bit [2:-1] vec = 4'b1001;
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bit btvar = 0;
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byte bvar = 0;
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shortint svar = 0;
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int ivar = 0;
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longint lvar = 0;
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initial begin
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if ((vec[-1] != 1) && (vec[0] != 0) &&
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(vec[1] != 0) && (vec[2] != 1)) begin
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$display("Failed to select vector bits correctly");
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$finish;
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end
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$display("Vec: ", vec);
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$display("Bit: ", btvar);
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$display("Byte: ", bvar);
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$display("Short: ", svar);
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$display("Int: ", ivar);
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$display("Long: ", lvar);
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$display("Monitor results:");
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$monitor("Time: ", $stime,
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"\n Bit: ", btvar,
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"\n Byte: ", bvar,
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"\n Short: ", svar,
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"\n Int: ", ivar,
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"\n Long: ", lvar);
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#1 btvar = 1;
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#1 bvar = 1;
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#1 svar = 1;
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#1 ivar = 1;
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#1 lvar = 1;
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end
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endmodule
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