23 lines
352 B
Verilog
23 lines
352 B
Verilog
module test();
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tri1 a;
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tri0 b;
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assign (pull1,pull0) a = 1'b0;
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assign (pull1,pull0) b = 1'b1;
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reg failed;
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initial begin
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failed = 0; #1;
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$display("a = %b, expect x", a); if (a !== 1'bx) failed = 1;
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$display("b = %b, expect x", b); if (b !== 1'bx) failed = 1;
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if (failed)
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$display("FAILED");
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else
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$display("PASSED");
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end
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endmodule
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