39 lines
713 B
Verilog
39 lines
713 B
Verilog
`timescale 1 ns / 1 ns
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module short(inout [7:0] p, input en);
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assign p = en ? 8'h55 : 8'hzz;
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endmodule
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module long(inout [15:0] p, input en);
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assign p = en ? 16'haaaa : 16'hzzzz;
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endmodule
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module main;
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wire [15:0] bus;
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reg l_en, s_en;
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integer fails=0;
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long l(.p(bus), .en(l_en));
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short s(.p(bus[7:0]), .en(s_en));
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initial begin
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// $dumpfile("tri.vcd");
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// $dumpvars(3,main);
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l_en = 0;
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s_en = 0;
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#10;
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l_en = 1;
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#10;
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$display("s.p = %4x", s.p);
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if (s.p !== 8'haa) fails=1;
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#10;
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l_en = 0;
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s_en = 1;
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#10;
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$display("l.p = %4x", l.p);
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if (l.p !== 16'hzz55) fails=2;
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#10;
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s_en = 0;
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#10;
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if (fails == 0) $display("PASSED");
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else $display("FAILED ",fails);
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end
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endmodule
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