29 lines
498 B
Verilog
29 lines
498 B
Verilog
module main;
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reg flag;
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reg [3:0] a, b;
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wire [4:0] Q = flag? a : b;
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initial begin
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flag = 1;
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a = 4'b1010;
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b = 4'b0101;
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#1 $display("%b = %b? %b : %b", Q, flag, a, b);
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if (Q !== 5'b01010) begin
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$display("FAILED -- Q=%b, flag=%b, a=%b", Q, flag, a);
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$finish;
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end
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flag = 0;
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#1 if (Q !== 5'b00101) begin
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$display("FAILED -- Q=%b, flag=%b, b=%b", Q, flag, b);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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