22 lines
423 B
Verilog
22 lines
423 B
Verilog
// Check that it is an error to declare a non-ANSI task port with implicit
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// packed dimensions if it is later redeclared as a packed struct typed
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// variable. Even if the size of the packed dimensions matches that of the size
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// of the struct.
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typedef struct packed {
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reg [31:0] x;
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reg [7:0] y;
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} T;
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module test;
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task t;
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input [47:0] x;
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T x;
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$display("FAILED");
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endtask
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initial t(10);
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endmodule
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