30 lines
575 B
Verilog
30 lines
575 B
Verilog
// Check that it is possible to declare the data type for a packed array type
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// task port before the direction for non-ANSI style port declarations.
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module test;
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typedef logic [7:0] T1;
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typedef T1 [3:0] T2;
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task t;
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T2 x;
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input x;
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if (x[0] == 1 && x[1] == 2 && x[2] == 3 && x[3] == 4 &&
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$bits(x) == $bits(T2)) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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endtask
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initial begin
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static T2 val;
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val[0] = 8'h1;
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val[1] = 8'h2;
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val[2] = 8'h3;
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val[3] = 8'h4;
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t(val);
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end
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endmodule
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