17 lines
313 B
Verilog
17 lines
313 B
Verilog
// Check that declaring a real typed variable for a signal that was previously
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// declared as a non-ANSI task port is an error. Even if the types for both
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// declarations are the same.
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module test;
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task t;
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output real x;
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real x;
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$display("FAILED");
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endtask
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real y;
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initial t(y);
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endmodule
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