70 lines
1.4 KiB
Verilog
70 lines
1.4 KiB
Verilog
/*
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* Check declarations and repeat declarations in nested modules.
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*/
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timeunit 100us;
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timeprecision 1us;
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// A local time unit is OK.
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module check_tu_nest;
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timeunit 10us;
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module nested;
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timeunit 100us;
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timeunit 100us;
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endmodule
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timeunit 10us;
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endmodule
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// A local time precision is OK.
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module check_tp_nest;
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timeprecision 10us;
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module nested;
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timeprecision 1us;
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timeprecision 1us;
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endmodule
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timeprecision 10us;
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endmodule
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// Both a local time unit and precision are OK.
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module check_tup_nest;
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timeunit 10us;
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timeprecision 10us;
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module nested;
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timeunit 100us;
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timeprecision 1us;
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timeunit 100us;
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timeprecision 1us;
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endmodule
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timeunit 10us;
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timeprecision 10us;
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endmodule
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// Both a local time unit and precision are OK (check both orders).
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module check_tpu_nest;
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timeprecision 10us;
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timeunit 10us;
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module nested;
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timeprecision 1us;
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timeunit 100us;
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timeprecision 1us;
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timeunit 100us;
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endmodule
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timeprecision 10us;
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timeunit 10us;
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endmodule
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module check2;
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initial begin
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$printtimescale(check_tu_nest);
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$printtimescale(check_tp_nest);
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$printtimescale(check_tup_nest);
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$printtimescale(check_tpu_nest);
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$display("");
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$printtimescale(check_tu_nest.nested);
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$printtimescale(check_tp_nest.nested);
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$printtimescale(check_tup_nest.nested);
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$printtimescale(check_tpu_nest.nested);
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end
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endmodule
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