33 lines
555 B
Verilog
33 lines
555 B
Verilog
module mod #(
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parameter A = 1,
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localparam B = A + 1,
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parameter C = B - 1
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) (
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input [A-1:0] a,
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input [B-1:0] b,
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input [C-1:0] c
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);
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endmodule
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module top();
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reg [3:0] a = 'ha;
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reg [4:0] b = 'hb;
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reg [5:0] c = 'hc;
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mod #(4, 6) m(a, b, c);
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initial begin
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$display("%0d %0d %0d", m.A, m.B, m.C);
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$display("%0d %0d %0d", $bits(m.a), $bits(m.b), $bits(m.c));
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if (m.A === 4 && $bits(m.a) === 4
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&& m.B === 5 && $bits(m.b) === 5
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&& m.C === 6 && $bits(m.c) === 6)
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$display("PASSED");
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else
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$display("FAILED");
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end
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endmodule
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