23 lines
379 B
Verilog
23 lines
379 B
Verilog
// Check that it is possible to omit a dimensions in a foreach loop by not
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// specifying a loop identifiers for the dimension.
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module test;
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logic a[2][3][4];
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int k = 0;
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initial begin
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foreach(a[i,,j]) begin
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$display(i, j);
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k++;
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end
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if (k == 8) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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