22 lines
347 B
Verilog
22 lines
347 B
Verilog
// Check that foreach loops without an index list work as expected. This is not
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// particularly useful, but it is legal code.
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module test;
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logic a[10];
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int i = 0;
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initial begin
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foreach(a[]) begin
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i++;
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end
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if (i == 0) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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