40 lines
578 B
Verilog
40 lines
578 B
Verilog
// Check that `super` keyword can be used to access members of the base class
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class B;
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int x, y;
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task set_y;
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y = 2000;
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endtask
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function bit check_x;
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return x === 1000;
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endfunction
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endclass
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class C extends B;
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byte x, y;
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task set_x;
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super.x = 1000;
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endtask
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function bit check_y;
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return super.y === 2000;
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endfunction
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endclass
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module test;
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C c;
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initial begin
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c = new;
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c.set_x;
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c.set_y;
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if (c.check_x() && c.check_y()) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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