26 lines
464 B
Verilog
26 lines
464 B
Verilog
// Check that the signedness of class properties are handled correctly when
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// accessing the property on a class object and passing it to a system function.
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module test;
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class C;
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shortint s = -1;
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bit [15:0] u = -1;
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endclass
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C c;
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string s;
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initial begin
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c = new;
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s = $sformatf("%0d %0d", c.s, c.u);
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if (s == "-1 65535") begin
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$display("PASSED");
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end else begin
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$display("FAILED s=%s", s);
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end
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end
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endmodule
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